1. Field of the Invention
The present invention relates to snoop operation in an information processing device.
2. Description of Related Art
In recent years, multi-core design in which multiple CPUs are incorporated in a processor has been a mainstream architecture of PCs and embedded devices. Conventionally, the enhancement of the performance of CPUs has been achieved by scaling and increase in the number of pipeline stages through process shrink to increase frequencies. At the 130 to 90-nm processes, however, the progress of scaling through process shrink was slowed down and the leakage power becomes very large in operation at enhanced frequency. Therefore, it has become difficult to apply the process shrink because of the restrictions of cooling cost and battery life. One of technologies for solving this problem is multi-core. In multi-core systems, the performance is enhanced by parallel processing of multiple CPUs and thus it is unnecessary to enhance frequencies and power consumption can be suppressed.
To enhance the efficiency of parallel processing by multi-core systems, it is required to maintain cache coherency. Usually, CPUs have a cache for accelerating instructions and data access. Writing to a cache by CPU is locally executed and the latest data does not exist in a memory and often exists only in a cache. Data may be shared between CPUs. When the latest data written to the cache of another CPU cannot be directly referred to, the following procedure must be taken: the CPU is interrupted and the latest data is written back to the memory and then it is cached again. This leads to significant degradation in performance. To cope with this, it is important to be capable of directly referring to the latest date written to the cache of another CPU (=the maintenance of cache coherency) in multi-core systems.
As protocols for maintaining the cache coherency, the MESI protocol and the MOESI protocol are known. In these protocols, snoop operation is defined. Snoop operation refers to a series of processing in which some CPU makes a request to another CPU as required when the cache thereof is updated and the requested CPU updates its own cache and sends back a response.
In parallel processing in multi-core systems, data is shared between CPUs and thus a large number of snoop operations are carried out. This makes it very difficult to debug programs. Usually, programs are debugged as follows: a break point is set and the CPU is stopped; and then the values of the cache, registers, and memory are checked to identify the cause of a bug. In multi-core systems, however, these values are updated by a program running on another CPU even though some CPU is stopped. One of conventional technologies for solving this problem is disclosed in Patent Document 1. In the technology disclosed in Patent Document 1, it can be chosen whether to stop only the CPU that caused the exception or all the CPUs at the time of a break point exception. The values of the cache, registers, and memory can be prevented from being thereafter updated by stopping all the CPUs.    [Patent Document 1] Japanese Unexamined Patent Publication No. Hei 6 (1994)-332747
When another CPU is stopped based on a break point exception caused in some CPU, it takes several cycles to several tens of cycles or so and the other CPU cannot be immediately stopped. This number of cycles depends on CPU or the implementation of a debug controller; however, there is a tendency that a larger number of cycles are required at a higher frequency. When a large number of snoop operations are carried out during this period, the state of a cache is updated by a snoop from another CPU even though the CPU for which a break point is set in a program is stopped. Even though an erroneous result is found in the cache after the CPU is stopped, it is difficult to identify when the bug slipped in. Therefore, it is desirable to provide a technology for efficiently debugging programs with respect to snoop operation in information processing devices.